C. Dunn, Ç. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, Tamer San
{"title":"闪存EPROM干扰机制","authors":"C. Dunn, Ç. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, Tamer San","doi":"10.1109/RELPHY.1994.307820","DOIUrl":null,"url":null,"abstract":"Analyses have been performed on floating-gate avalanche-injection MOS transistor (FAMOS) devices which have been subjected to write/erase cycling, resulting in hole injection into the tunnel dielectric. Theoretical and experimental analysis of these devices have shown that the bits which exhibit fast erase due to these trapped holes are highly modulated by the field across the tunnel dielectric. Two distinct disturb mechanisms, one of which is heavily impacted by write/erase cycling, have been evaluated with regards to their field and temperature dependencies and empirical models have been developed for both mechanisms.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"121 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"56","resultStr":"{\"title\":\"Flash EPROM disturb mechanisms\",\"authors\":\"C. Dunn, Ç. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, Tamer San\",\"doi\":\"10.1109/RELPHY.1994.307820\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Analyses have been performed on floating-gate avalanche-injection MOS transistor (FAMOS) devices which have been subjected to write/erase cycling, resulting in hole injection into the tunnel dielectric. Theoretical and experimental analysis of these devices have shown that the bits which exhibit fast erase due to these trapped holes are highly modulated by the field across the tunnel dielectric. Two distinct disturb mechanisms, one of which is heavily impacted by write/erase cycling, have been evaluated with regards to their field and temperature dependencies and empirical models have been developed for both mechanisms.<<ETX>>\",\"PeriodicalId\":276224,\"journal\":{\"name\":\"Proceedings of 1994 IEEE International Reliability Physics Symposium\",\"volume\":\"121 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-04-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"56\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.1994.307820\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.1994.307820","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analyses have been performed on floating-gate avalanche-injection MOS transistor (FAMOS) devices which have been subjected to write/erase cycling, resulting in hole injection into the tunnel dielectric. Theoretical and experimental analysis of these devices have shown that the bits which exhibit fast erase due to these trapped holes are highly modulated by the field across the tunnel dielectric. Two distinct disturb mechanisms, one of which is heavily impacted by write/erase cycling, have been evaluated with regards to their field and temperature dependencies and empirical models have been developed for both mechanisms.<>