6500V 4H-SiC功率dmosfet的仿真、制作与表征

Shiyan Li, Hao Liu, Run-Hua Huang, Y. Tao, Qiang Liu, Yun Li, S. Bai
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引用次数: 4

摘要

利用60μm厚、1.0×1015 cm−3掺杂的漂移层成功制备了击穿电压高于8.0 kV的4H-SiC功率dmosfet。本文报道了4H-SiC dmosfet的仿真、制备及其电学特性。从测试的MOSFET中提取了20 cm2/Vs的有效沟道迁移率峰值。在VGS为20V时,测量到的特定导通电阻为80 mΩ-cm2,与先前报道的值相比,Ron sp降低了32%。在漏极偏置为8.0 kV的情况下,从一个有源面积为1.0×10−2 cm2的4H-SiC DMOSFE中测量到的漏电流为12 μΑ。在本报告中,在测试PiN二极管中实现了四种新的端接结构(T1-T3)并进行了测试,以减少端接长度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Simulation, fabrication and characterization of 6500V 4H-SiC power DMOSFETs
4H-SiC power DMOSFETs with breakdown voltage higher than 8.0 kV has been successfully fabricated by using an 60μm-thick, 1.0×1015 cm−3 doped drift epilayer. In this paper, the simulation, the fabrication, and the electrical characteristics of 4H-SiC DMOSFETs were reported. A peak effective channel mobility of 20 cm2/Vs was extracted from a test MOSFET. A specific on-resistance of 80 mΩ-cm2 were measured with at a VGS of 20V, a 32% reduction in Ron sp, compared to a previously reported value. A leakage current of 12 μΑ was measured at a drain bias of 8.0 kV from a 4H-SiC DMOSFE with an active area of 1.0×10−2 cm2. In this report, four new termination structures (T1-T3) were implemented in test PiN diodes and tested, for a reduction of termination length.
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