Sub-90nm pitch Cu low-k interconnect etch solution using RF pulsing technology

J. Liao, Y. T. Lai, Stan Wan, B. Kuo, P. Gopaladasu, David Wei, S. Yao, Wesley L. Lin, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh
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引用次数: 2

Abstract

Self-aligned via (SAV) schemes are commonly used for back-end-of-line (BEOL) interconnect structures that have scaled to <; 90nm BEOL pitch [1]. In one implementation of this scheme, a TiN metal hard mask (MHM) is used for trench pattern definition, while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process using RF pulsing in a capacitively coupled etch reactor that provides a solution to both via distortion / striation and critical dimension (CD) bias loading. Electrical results will be discussed.
使用射频脉冲技术的90nm以下间距Cu低k互连蚀刻解决方案
自对准通孔(SAV)方案通常用于缩放到<;90nm BEOL间距[1]。在该方案的一种实现中,TiN金属硬掩模(MHM)用于沟槽图案定义,而互连过孔使用三层抗蚀剂掩模进行图图化,使过孔与底层沟槽线自对齐[2]。在这项工作中,我们描述了在电容耦合蚀刻反应器中使用RF脉冲的SAV蚀刻工艺,该工艺提供了通过扭曲/条纹和临界尺寸(CD)偏压加载的解决方案。电气结果将被讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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