PI under fill effect study for gold migration improvement in the high voltage COF assembly application

Abstract

As the trend in electronic devices keeps striding towards minimization, high speed, high resolution, and multi-functions, the electromigration problem in chip packages becomes unavoidable, which creates an unintended electrical connection between terminals and causes electrical short, especially for high voltage products with COF package application. The aim of this study is to find a solution to prevent the phenomena from occurring. Therefore, we introduce the methodology of “PI under fill” in the gold bumped wafers to prevent the Au-migration-induced short-circuit failure in the COF packages since the defect mode of “Au migration” is now seriously affecting the advance of the consumer product development. However, it is difficult to detect the defect mode during the whole packaging process line since only an extremely low content of the migrating ions exists in the meanwhile. Currently, some fine pitch cases have redesigned the bonding pads/bumps from linear to stagger layout in order to enlarge the bump spaces. However, this kind of design has its limitation due to higher pin count and reduced chip size requirements for the next generation devices. In this study, two lots of bumped wafers were taken for experiment by coating PI in the bump spaces to form electrical insulation between bumps. The results show that the PI appearance meets our expectation and with the application of the PI under fill in the bump spaces the COF packages can still maintain normal performance.