Design and characterization of a copper-pillar flip chip test vehicle for small form-factor packages using 28nm ELK die and bump-on-trace (BOT)

Abstract

Overview Current solder-based flip chip technology is limited in interconnect density because bump height and bump pitch have a fixed aspect ratio and cannot be sufficiently reduced due to manufacturing requirements such as coplanarity and underfill. As semiconductor dice are reduced in size as a result of wafer node-shrink, designs might become bump-limited unless bump pitch can be reduced proportionately. In addition, methodologies are needed to reduce the cost of flip chip designs, even if the designs are not pad-limited.