F. Arnaud, Nicolas Planes, O. Weber, V. Barral, S. Haendler, Philippe Flatresse, F. Nyer
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引用次数: 41
Abstract
This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.
本文介绍了超薄盒体(Ultra-Thin Box and Body, UTBB)技术在低电压下提供高速的优越性能。我们证明了由于平面背面栅极方案,晶体管能够维持完全的正向体偏置解决方案。在低复杂度电路上的硅测量表明,通过简单地选择合适的电源和体偏置耦合器(Vdd;Vbb)。然后提出了一个简单的开关能效模型,允许(Vdd;Vbb)耦合预测达到最小能量点。最后,我们展示了一个完整的CPU核心实现与UTBB,总功耗降低-30%和+40%的能源效率在相同的速度相对于散装技术,由于后门偏置效率。