Optimization of hierarchical SOC test time based on genetic algorithm

Abstract

Test time optimization is necessary for modular testing of hierarchical system-on-chip (SOC) that contain embedded IP core. In this paper, we consider the case of non-interactive design transfer between IP core vendor and IC integrator. We proposes a method based on genetic algorithm which can efficiently optimize the test time of hierarchical SOC. Utilizing international reference circuit provided by International Test conference 2002(ITCpsila02), we execute the experiment and results suggest that this method is superior than recently proposes methods for hierarchical SOC test time.