Tool commonality analysis for yield enhancement

Abstract

ULSI semiconductor processing today involves hundreds of process steps through various semiconductor processing tools. Any tool excursion could lead to serious and costly yield problems. Tool commonality among bad lots is a proven technique to identify the root cause of the problem. As the complexity of process and the number of process steps increase, it is a very challenging task to pin point which tool is the source of problem and at which process step it occurs. Taking advantage of electronic lot tracking systems, systematic tool commonality analysis is capable of effectively identifying the problem source. The critical elements of successful tool commonality analysis are discussed and summarized in this paper, including sample size selection, raw data classification, statistical analysis, time series and analysis of tools with multiple entry points within the same process flow. Several pitfalls of the analysis are identified and discussed. This analysis is successfully applied on a yield enhancement effort in an advanced volume manufacturing fab.