Selective co growth on Cu for void-free via fill

Jun-Fei Zheng, Philip Chen, Tomas H. Baum, R. Lieten, W. Hunks, S. Lippy, A. Frye, Weimin Li, James O'Neill, Jeff Xu, John Zhu, Jerry Bao, V. Machkaoutsan, M. Badaroglu, G. Yeap, G. Murdoch, J. Bommels, Z. Tokei
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引用次数: 6

Abstract

We report for the first time a highly selective CVD Co deposition on Cu to fill a 45nm diameter 3:1 aspect ratio via in a Cu dual damascene structure. We have achieved void-free Co fill of the via, demonstrating that a selective bottom-up via fill with Co is a potentially viable approach. Defect formation and control in the process and device integration are discussed. This selective process provides an opportunity to reduce via resistance and shrink the minimum metal 1 (M1) area for aggressive standard cell size scaling as needed for 7nm technology.
通过填充物在Cu上选择性co生长
本文首次报道了一种高选择性CVD Co沉积在Cu上,以填充直径为45nm、纵横比为3:1的Cu双damascene结构孔。我们已经实现了孔道的无孔洞Co填充,表明选择性的自下而上孔道填充Co是一种潜在可行的方法。讨论了工艺和设备集成中的缺陷形成和控制。这种选择性工艺提供了减少电阻和缩小最小金属1 (M1)面积的机会,以满足7nm技术所需的标准电池尺寸缩放。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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