A 5-Gbps Test System for Wafer-Level Packaged Devices

A. Majid, D. Keezer
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引用次数: 2

Abstract

This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a plusmn 18-ps timing accuracy. The generated signals exhibit low jitter ( ~ 35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.
晶圆级封装器件的5gbps测试系统
本文介绍了一种经济的晶圆级封装逻辑器件高速测试方法。该解决方案假设设备具有内置的自测功能,从而减少了所需的外部测试仪器的复杂性。一个独立的微型测试仪连接到晶圆探测卡的顶部,发送和接收多个高速(2-5 Gbps)信号。为了保持低成本,测试人员使用现成的组件。然而,它的性能在某些方面超过了传统的自动化测试设备(ATE)。测量表明,测试仪产生5-Gbps信号与正负18-ps定时精度。生成的信号表现出低抖动(~ 35 ps),并且具有约60 ps的上升时间。信号捕获也显示出类似的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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