Process Window Enhancement of Via Holes for Fine Pitch RDL by Design Optimization

Abstract

Wafer-level packaging with high density fan-out (HDFO) requires multiple redistribution layers (RDL) to handle the high-density interconnections and the large data transfer rates between chips in the package. Decreasing the critical dimension (CD) of lines in an RDL enables electrical performance that meets the system requirements with fewer layers, which lowers costs. Reducing RDL line CD also requires reducing the CD for the interconnections (via) in the dielectric layer. The lithographic imaging of small via openings presents multiple challenges. The first challenge is obtaining good lithographic performance of the permanent photosensitive polymer used to define the dielectric layer between the metal layers. The second challenge is the increased difficulty of imaging a via compared to imaging a line of the same critical dimension, due to both the smaller area of light modulation used to transfer the pattern and the diffraction of the light as it passes through the imaging system. To address these challenges, in this study we relax the dimension of the round via in the direction parallel to the RDL line, creating an elongated via. This design change significantly improves the intensity distribution at the wafer (aerial image) for the via, which increases the effective process window [1].In this paper we investigate the performance of a negative-tone photosensitive permanent dielectric for 1.0 - 2.0 pm CD vias. The permanent photosensitive polymer material is used in a dual damascene RDL process, and previous studies have demonstrated sufficient resolution and process capability [2]. We investigate multiple length-to-width ratios for the vias using both lithographic simulation and experiment to determine the optimal via shape to maximize the process window. In this paper we present both modeled and experimental lithography test results. The process window for the elongated vias shows significant improvement compared to the symmetric via for fine-pitch RDL applications.