A new charge-trapping technique to extract SILC-trap time constants in SiO/sub 2/

Abstract

A new experimental technique for investigating the trapping-detrapping time constants for electrons at stress-induced defects in the silicon oxide is presented. The new technique is based on the gate-stress measurement for flash memories, with the application of a pulsed gate voltage. Data for 512 Kbit NOR-flash arrays are presented, and analyzed by analytical and Monte Carlo models for the trap-assisted tunneling mechanism under pulsed conditions. Comparison between experimental data and calculations for selected cells allows for an estimation of the energy and spatial depth of the oxide traps