MOS interface and channel engineering for high-mobility Ge/III-V CMOS

S. Takagi, R. Zhang, S. Kim, N. Taoka, M. Yokoyama, Junkyo Suh, R. Suzuki, M. Takenaka
{"title":"MOS interface and channel engineering for high-mobility Ge/III-V CMOS","authors":"S. Takagi, R. Zhang, S. Kim, N. Taoka, M. Yokoyama, Junkyo Suh, R. Suzuki, M. Takenaka","doi":"10.1109/IEDM.2012.6479085","DOIUrl":null,"url":null,"abstract":"CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for improving the channel mobility and the MOS interface properties with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. HfO2/Al2O3/GeOx/Ge gate stacks exhibit record high electron and hole mobility under EOT of 0.76 nm. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm. The results of low Dit HfO2/Al2O3/InGaAs stacks with CET of 1.08 nm are also presented. A strategy to enhance electron mobility in InGaAs MOSFETs on a basis of physical understanding of the MOS interface properties including high Dit inside the conduction band is also addressed.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"322 1","pages":"23.1.1-23.1.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6479085","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 43

Abstract

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for improving the channel mobility and the MOS interface properties with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. HfO2/Al2O3/GeOx/Ge gate stacks exhibit record high electron and hole mobility under EOT of 0.76 nm. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm. The results of low Dit HfO2/Al2O3/InGaAs stacks with CET of 1.08 nm are also presented. A strategy to enhance electron mobility in InGaAs MOSFETs on a basis of physical understanding of the MOS interface properties including high Dit inside the conduction band is also addressed.
高迁移率Ge/III-V CMOS的MOS接口和通道工程
在Si衬底上利用高迁移率III-V/Ge通道的CMOS有望成为未来高性能低功耗高级lsi的有前途的器件之一,因为它具有增强的载流子传输特性。然而,满足未来节点mosfet需求的Ge/III-V n-和pmosfet的器件/工艺/集成技术尚未建立。在本文中,我们讨论了栅极堆栈和通道工程,以提高通道迁移率和MOS接口性能,重点是薄EOT和超薄体,这是未来节点的必备条件。对于Ge mosfet,等离子体后氧化形成的GeOx/Ge界面可实现薄EOT、低Dit和高迁移率。在0.76 nm的EOT下,HfO2/Al2O3/GeOx/Ge栅极具有较高的电子和空穴迁移率。对于III-V型mosfet,具有MOS界面缓冲层的超薄InAs通道在3 nm的InAs厚度下具有较高的电子迁移率。本文还介绍了低Dit的HfO2/Al2O3/InGaAs堆的效果,CET为1.08 nm。在对MOS界面特性(包括导带内的高Dit)的物理理解的基础上,提出了提高InGaAs mosfet中电子迁移率的策略。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信