Advanced integrated metallization enables 3D-IC TSV scaling

2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI:10.1109/IITC-MAM.2015.7325620

Jengyi Yu, S. Gopinath, P. Nalla, Matthew Thorum, L. Schloss, D. M. Anjos, Prashant Meshram, G. Harm, Joe Richardson, T. Mountsier

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引用次数: 8

Abstract

Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.

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先进的集成金属化使3D-IC TSV缩放

创新的解决方案已经开发出来，以解决具有小尺寸和高纵横比的硅通孔(TSV)金属化的挑战。我们展示了一种先进的金属化方案，包括金属屏障和种子的保形膜沉积，具有良好的侧壁覆盖率，以实现高纵横比(10:1至20:1)的小尺寸(10至1 μm) TSV的无空隙铜填充。此外，它还减少了现场金属厚度，从而显著降低了金属化和后续CMP的成本。与传统的PVD势垒种子相比，采用这种工艺集成方案制备的tsv具有更高的击穿电压和更低的泄漏电流。经过400°C退火和热循环后，性能没有下降。性能的提高是由于形成了无针孔的金属阻挡层，具有良好的侧壁覆盖率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)

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