Improved sub-10-nm CMOS devices with elevated source/drain extensions by tunneling si-selective-epitaxial-growth

Abstract

Improved sub-10-nm CMOS devices have been investigated by the elevated source/drain extensions (eSDE) using the tunneling silicon selective epitaxial growth (Si-SEG) in the reverse-order source/drain formation. In this eSDE technology, the SEG-Si thickness for eSDE region is precisely controlled by the self-limited Si-SEG process within a narrow slit underneath a SiN sidewall film. Moreover, the SEG-Si film for the elevated source/drain (eS/D) region is also achieved simultaneously. As the results of simultaneously-reduced short-channel effect and parasitic resistance, the Ioff-CV/I characteristics are remarkably improved for both n- and pMOSFETs, as compared with published sub-10-nm planar bulk CMOS devices