Advanced high density interconnection substrate for mobile platform application

C. Romero, Seungwook Park, Y. Kweon, M. Park
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引用次数: 4

Abstract

The faster market trend towards smart phones with more advanced computing ability and connectivity will drive the greater need to incorporate more functionality in smaller space by integrating more components and functional blocks into convergent systems in form of chip-level (SOC) or die-level (SIP) packaging. As feature size continues to shrink, it requires combination of stringent design requirements which all interact in order to achieve the desired performance. Also, various limitations will arise in the design of the PCB in terms of size and signal integrity. The substrate or PCB plays critical role in the miniaturization of the overall system and the final application's electrical performance. Given the extreme routing requirement of each component package with high I/O pins and fine pitch area array, the conventional HDI substrate pose some design challenges and limitations. In order to increase the routing density, it often requires smaller trace width and micro via diameter and even the need of adding more metal layers. These, however, will dramatically increase the cost and more reliability risk is expected. In this paper, we present a new generation substrate that could meet the mobile platform requirement by proposing an advanced ultra fine metal resolution substrate. It will demonstrate its high density interconnect capability in a basic 4-layer stack-up structure. One of its advanced features is the ability to adjust board and interconnection impedance in order to optimize signal integrity and more routing capability for dense mobile platform layouts. It will also demonstrate that organic-based substrate may also achieve tighter routing density using limited number of metal layers at smaller and thinner form factor while maintaining the desired signal integrity performance as compared to conventional 8-layer or 10-layer HDI PCBs. Details of electrical simulation and measurement of electrical parameters are also presented and discussed.
用于移动平台应用的先进高密度互连基板
智能手机的市场趋势越来越快,具有更先进的计算能力和连接性,这将推动更大的需求,通过将更多的组件和功能模块以芯片级(SOC)或芯片级(SIP)封装的形式集成到融合系统中,在更小的空间中整合更多功能。随着特征尺寸的不断缩小,它需要结合严格的设计要求,这些要求相互作用才能达到预期的性能。此外,PCB在尺寸和信号完整性方面的设计也会出现各种限制。基板或PCB在整个系统的小型化和最终应用的电气性能中起着至关重要的作用。考虑到每个组件封装对高I/O引脚和细间距区域阵列的极端布线要求,传统的HDI基板带来了一些设计挑战和局限性。为了增加布线密度,通常需要更小的走线宽度和微通孔直径,甚至需要添加更多的金属层。然而,这些将大大增加成本和更多的可靠性风险。本文通过提出一种先进的超细金属分辨率基板,提出了满足移动平台要求的新一代基板。它将在基本的4层堆叠结构中展示其高密度互连能力。其先进的功能之一是能够调整板和互连阻抗,以优化信号完整性和更密集的移动平台布局的路由能力。它还将证明,与传统的8层或10层HDI pcb相比,有机基板也可以在更小更薄的外形上使用有限数量的金属层来实现更紧密的布线密度,同时保持所需的信号完整性性能。详细介绍了电学仿真和电学参数的测量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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