{"title":"A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS","authors":"Zhe Yu, Yuhua Liang, Shubin Liu","doi":"10.1016/j.mejo.2021.105253","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":18617,"journal":{"name":"Microelectron. J.","volume":"45 1","pages":"105253"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectron. J.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1016/j.mejo.2021.105253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
5mhz - bw 71.7 db SNDR两步混合域ADC, 65nm CMOS
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