Yong Cai, Z. Cheng, W.C.-W. Tang, Kevin J. Chen, K. Lau
{"title":"Monolithic integration of enhancement-and depletion-mode AlGaN/GaN HEMTs for GaN digital integrated circuits","authors":"Yong Cai, Z. Cheng, W.C.-W. Tang, Kevin J. Chen, K. Lau","doi":"10.1109/IEDM.2005.1609468","DOIUrl":null,"url":null,"abstract":"We demonstrate a novel technique for monolithic integration of enhancement and depletion-mode AlGaN/GaN HEMTs using CF4 plasma treatment. Direct-coupled FET logic circuits such as an E/D HEMT inverter and a 17-stage ring oscillator are demonstrated in GaN system for the first time. At a supply voltage (VDD)of 1.5V, the fabricated E/D inverter shows an output logic swing of 1.25V, logic-low noise margin of 0.21V and logic-high noise margin of 0.51V. The fabricated ring oscillator shows a minimum delay of 130 ps/stage at V DD = 3.5 V, and a minimum power-delay product of 0.113 pJ/stage at VDD = 1 V","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"48 1","pages":"4 pp.-774"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609468","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23
Abstract
We demonstrate a novel technique for monolithic integration of enhancement and depletion-mode AlGaN/GaN HEMTs using CF4 plasma treatment. Direct-coupled FET logic circuits such as an E/D HEMT inverter and a 17-stage ring oscillator are demonstrated in GaN system for the first time. At a supply voltage (VDD)of 1.5V, the fabricated E/D inverter shows an output logic swing of 1.25V, logic-low noise margin of 0.21V and logic-high noise margin of 0.51V. The fabricated ring oscillator shows a minimum delay of 130 ps/stage at V DD = 3.5 V, and a minimum power-delay product of 0.113 pJ/stage at VDD = 1 V