J. Alfaro-Barrantes, M. Mastrangeli, D. Thoen, J. Bueno, J. Baselmans, P. Sarro
{"title":"Fabrication of Al-Based Superconducting High-Aspect Ratio TSVS for Quantum 3D Integration","authors":"J. Alfaro-Barrantes, M. Mastrangeli, D. Thoen, J. Bueno, J. Baselmans, P. Sarro","doi":"10.1109/MEMS46641.2020.9056165","DOIUrl":null,"url":null,"abstract":"We describe a microfabrication process that, thanks to a specifically tailored sidewall profile, enables for the first-time wafer-scale arrays of high-aspect ratio through-silicon vias (TSVs) coated with DC-sputtered Aluminum, achieving at once superconducting and CMOS-compatible 3D interconnects. Void-free conformal coating of up to $500\\ \\mu\\mathrm{m}$-deep and $50\\ \\mu\\mathrm{m}$-wide vias with a mere $2\\ \\mu\\mathrm{m}$-thick layer of Al, a widely available metal in for IC manufacturing, was demonstrated. Single-via electric resistance as low as $468 \\mathrm{m}\\Omega$ at room temperature and superconductivity at 1.25 K were measured by a cross-bridge Kelvin resistor structure. This work establishes the fabrication of functional superconducting interposers suitable for 3D integration of high-density silicon-based quantum computing architectures.","PeriodicalId":6776,"journal":{"name":"2020 IEEE 33rd International Conference on Micro Electro Mechanical Systems (MEMS)","volume":"25 1","pages":"932-935"},"PeriodicalIF":0.0000,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 33rd International Conference on Micro Electro Mechanical Systems (MEMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MEMS46641.2020.9056165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We describe a microfabrication process that, thanks to a specifically tailored sidewall profile, enables for the first-time wafer-scale arrays of high-aspect ratio through-silicon vias (TSVs) coated with DC-sputtered Aluminum, achieving at once superconducting and CMOS-compatible 3D interconnects. Void-free conformal coating of up to $500\ \mu\mathrm{m}$-deep and $50\ \mu\mathrm{m}$-wide vias with a mere $2\ \mu\mathrm{m}$-thick layer of Al, a widely available metal in for IC manufacturing, was demonstrated. Single-via electric resistance as low as $468 \mathrm{m}\Omega$ at room temperature and superconductivity at 1.25 K were measured by a cross-bridge Kelvin resistor structure. This work establishes the fabrication of functional superconducting interposers suitable for 3D integration of high-density silicon-based quantum computing architectures.