Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure

Abstract

Trap density (D_it) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted D_it with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the D_it extracted by conductance method was 1~2×10¹² cm^-2eV^-1 in E_c-E_T of 0.15~0.35 eV. The simulation results of I_BL-V_CG and C-V_CG based on the D_it were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.