ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training

IF 1.9 4区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Design & Test Pub Date : 2023-12-01 DOI:10.1109/MDAT.2023.3309743

K. Neethu, K. C. S. Shahana, Rekha K. James, John Jose, Sumit K. Mandal

引用次数: 0

Abstract

Editor’s notes: In this article, an architecture for in-memory computing (IMC)-based 2.5-D systems with multiple Network-on-Package (NoP) components is proposed. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto, Barcelona Supercomputing Center, Spain —Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden —Sujay Deb, IIIT Delhi, India

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元素:用于深度神经网络训练的基于imc的2.5维加速器的节能Multi-NoP架构

编者按:在本文中，提出了一种基于内存计算(IMC)的具有多个包上网络(NoP)组件的2.5维系统体系结构。-Mahdi Nikdast，美国科罗拉多州立大学-Miquel Moreto，西班牙巴塞罗那超级计算中心-Masoumeh (Azin) Ebrahimi，瑞典皇家理工学院-Sujay Deb，印度德里IIIT

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Design & Test COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-ENGINEERING, ELECTRICAL & ELECTRONIC

CiteScore

3.80

自引率

5.00%

发文量

期刊介绍： IEEE Design & Test offers original works describing the models, methods, and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews, and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy-efficient design, electronic design automation tools, practical technology, and standards.