Wafer level LED packaging with integrated DRIE trenches for encapsulation

Abstract

A novel encapsulation process for wafer level LED arrays is presented. In this process, 4 inch P-type single crystal silicon wafers served as the substrates for flip-chip mountable LED chips. The wafer substrates were fabricated by wafer level lithography and plating process. An UV curable epoxy was applied as the encapsulant. The encapsulation process takes advantage of square trenches fabricated by deep reaction ion etching (DRIE) process as barriers to limit the spread of the epoxy encapsulant, and can adjust the geometry of the encapsulation via controlling the volume of the epoxy and the dimension of the trenches. The packaging and encapsulation process of LED arrays were completed on wafer level. LED packages can be directly obtained after wafer dicing.