Performance and limitations of 65 nm CMOS for integrated RF power applications

Abstract

In this study, we present the first measurements of the RF power performance of 65 nm CMOS for different voltages and layouts. We demonstrate that the 65 nm technology node is capable of achieving PAE values greater than 50% at 8 GHz, with Pout scalable to about 17 dBm. This is of interest for many applications. Greater performance is expected by optimizing the layout to minimize interconnect resistance