The design of the cache crossbar based on OpenSPRAC architecture

Abstract

Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache crossbar to exchange the data in the L2 cache banks. The multi cores can communicate among each other core by sharing the data in the L2 cache banks. And with the analysis of the CCX, this paper provides a protocol for connecting multi cores and cache banks. The cache crossbar is implemented in SMIC 0.13 mum with design compiler and can run at 200 MHz.