Sheng-Feng Hsiao, Ming-Kun Chen, Yi-Lung Lin, Yu-Jung Huang, S. Fu
{"title":"Co-simulation of capacitive coupling pads assignment for capacitive coupling interconnection applications","authors":"Sheng-Feng Hsiao, Ming-Kun Chen, Yi-Lung Lin, Yu-Jung Huang, S. Fu","doi":"10.1109/IMPACT.2011.6117216","DOIUrl":null,"url":null,"abstract":"Three dimensions packaging provides a very promising technology for the effective integration of complex systems: devices that are optimally implemented with various different technologies can be separately manufactured and then stacked and connected by means of efficient vertical interconnections over a very short range; this provides most of the benefits of inter-chips for high-bandwidth with a reasonable cost and short development time in the advance of CMOS processes and assembly. This study presents the co-simulation of capacitive coupling pads assignment for the capacitive coupling interconnection. The modelling of a close capacitive coupling interconnection pad is represented by a lumped circuit. The coupling pads of parasitic capacitance are one of the parasitic parameters. The FEM (finite element method) tools simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. A comparison between simulated and measured circuit performance was shown for a RLC-elements, and qualitative accuracy was obtained. HSPICE tools are applied for the circuit simulations using the equivalent model of coupling pads. Based on the findings of this work, co-simulation methods can reduce simulation time dramatically, the coupling pads assignment can be translated to HSPICE model.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"8 1","pages":"347-350"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMPACT.2011.6117216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Three dimensions packaging provides a very promising technology for the effective integration of complex systems: devices that are optimally implemented with various different technologies can be separately manufactured and then stacked and connected by means of efficient vertical interconnections over a very short range; this provides most of the benefits of inter-chips for high-bandwidth with a reasonable cost and short development time in the advance of CMOS processes and assembly. This study presents the co-simulation of capacitive coupling pads assignment for the capacitive coupling interconnection. The modelling of a close capacitive coupling interconnection pad is represented by a lumped circuit. The coupling pads of parasitic capacitance are one of the parasitic parameters. The FEM (finite element method) tools simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. A comparison between simulated and measured circuit performance was shown for a RLC-elements, and qualitative accuracy was obtained. HSPICE tools are applied for the circuit simulations using the equivalent model of coupling pads. Based on the findings of this work, co-simulation methods can reduce simulation time dramatically, the coupling pads assignment can be translated to HSPICE model.