A 65nm NOR flash technology with 0.042/spl mu/m/sup 2/ cell size for high performance multilevel application

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI:10.1109/IEDM.2005.1609490

G. Servalli, D. Brazzelli, E. Camerlenghi, G. Capetti, S. Costantini, C. Cupeta, D. DeSimone, A. Ghetti, T. Ghilardi, P. Gulli, M. Mariani, A. Pavan, R. Somaschini

引用次数: 24

Abstract

A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS

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一种65nm NOR闪存技术，电池尺寸为0.042/spl mu/m/sup 2/，适用于高性能多级应用

65nm NOR闪存技术首次用于1bit/cell和2bit/cell产品，该技术具有真正的10lambda2, 0.042mum2电池。先进的193nm光刻技术，浮动栅自对准STI，钴盐化和三级铜金属化使其与高密度高性能1.8V CMOS集成

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

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