CMOS 16FF Digital Power Amplifier RF Reliability Characterization

Abstract

This letter describes the reliability characterization process of switched capacitor digital power amplifier (SCDPA) manufactured in CMOS acrlong 16FF technology. Power amplifiers (PAs) operate at RF frequencies (2.4 and 5–7 GHz) in which the instantaneous voltage on the transistor terminals might exceed the maximum rated voltage, Vmax allowed by the process technology. Since the available technology models for reliability degradation under RF conditions are limited, a detailed design analysis for possible failure mechanisms was done, followed by product data collection while operating in RF. In this letter, we describe this process, including SCDPA reliability risk assessment and stress experiments. We explain how in SCDPA the VDD voltage is critical for failure acceleration and not the output power (as in analog power amplifier (PA). We also show that the initial design suffered from pMOS negative bias temperature instability (NBTI) which resulted in 2nd harmonics degradation. The NBTI issue was overcome by a novel design in which the bulk voltage is dynamically changed to lower the effective source–gate voltage (Vsg) on the SCDPA pMOS transistors. To stress the SCDPA, we used a setup in which the SCDPA transmits a continuous waveform (CW) along with voltage and temperature acceleration. Finally, we show how the dynamic bulk voltage solution was successful in overcoming the NBTI degradation.