A 15.5-ENOB 335 mVPP-Linear-Input-Range 4.7-GΩ-Input-Impedance CT-ΔΣM Analog Front-End With Embedded Low-Frequency Chopping

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2023-09-25 DOI:10.1109/LSSC.2023.3318815

Yijie Li;Weiqi Zhi;Yuying Li;Jianhong Zhou;Zhiliang Hong;Jiawei Xu

{"title":"A 15.5-ENOB 335 mVPP-Linear-Input-Range 4.7-GΩ-Input-Impedance CT-ΔΣM Analog Front-End With Embedded Low-Frequency Chopping","authors":"Yijie Li;Weiqi Zhi;Yuying Li;Jianhong Zhou;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2023.3318815","DOIUrl":null,"url":null,"abstract":"This article presents a second-order continuous-time delta-sigma (CT-\n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n)-based analog front-end (AFE) for biopotential sensor interfaces. High linearity is achieved by using a current balanced \n<inline-formula> <tex-math>$G_{m,1}$ </tex-math></inline-formula>\n input stage with gain-boosting and cascode techniques. Low-frequency chopping embedded in gain-boosting OTAs breaks the limitation of chopping frequency in conventional CT-\n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n ADCs and mitigates flicker noise without reducing the input impedance. In the second stage, the closed-loop \n<inline-formula> <tex-math>$G_{m,2}$ </tex-math></inline-formula>\n-OTA-C proportional integrator (PI) relaxes the linearity requirements of the OTA and eliminates the additional active adder. Fabricated in a standard 0.18-\n<inline-formula> <tex-math>$\\mu \\text{m}$ </tex-math></inline-formula>\n CMOS technology, this direct-digitization AFE achieves 94.9-dB peak SNDR, \n<inline-formula> <tex-math>$335 \\rm mV_{pp}$ </tex-math></inline-formula>\n linear input range, and 4.7-\n<inline-formula> <tex-math>$\\text{G}\\Omega $ </tex-math></inline-formula>\n input impedance at 50 Hz with \n<inline-formula> <tex-math>$64\\times $ </tex-math></inline-formula>\n reduction in the chopping frequency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"265-268"},"PeriodicalIF":2.2000,"publicationDate":"2023-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10261423/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

This article presents a second-order continuous-time delta-sigma (CT-

$\Delta \Sigma $

)-based analog front-end (AFE) for biopotential sensor interfaces. High linearity is achieved by using a current balanced

$G_{m,1}$

input stage with gain-boosting and cascode techniques. Low-frequency chopping embedded in gain-boosting OTAs breaks the limitation of chopping frequency in conventional CT-

$\Delta \Sigma $

ADCs and mitigates flicker noise without reducing the input impedance. In the second stage, the closed-loop

$G_{m,2}$

-OTA-C proportional integrator (PI) relaxes the linearity requirements of the OTA and eliminates the additional active adder. Fabricated in a standard 0.18-

$\mu \text{m}$

CMOS technology, this direct-digitization AFE achieves 94.9-dB peak SNDR,

$335 \rm mV_{pp}$

linear input range, and 4.7-

$\text{G}\Omega $

input impedance at 50 Hz with

$64\times $

reduction in the chopping frequency.

查看原文本刊更多论文

15.5-ENOB 335 mVPP线性输入范围4.7-GΩ-输入阻抗CT-Δ∑M模拟前端，带嵌入式低频斩波

本文提出了一种用于生物电位传感器接口的基于二阶连续时间Δ-∑（CT-$\delta\sigma$）的模拟前端（AFE）。通过使用具有增益提升和级联技术的电流平衡$G_{m，1}$输入级来实现高线性度。嵌入增益提升OTA中的低频斩波打破了传统CT-$\Delta\Sigma$ADC中斩波频率的限制，并在不降低输入阻抗的情况下减轻了闪烁噪声。在第二阶段中，闭环$G_{m，2}$-OTA-C比例积分器（PI）放松了OTA的线性要求，并消除了额外的有源加法器。该直接数字化AFE采用标准的0.18-$\mu\text｛m｝$CMOS技术制造，在50Hz下实现94.9dB峰值SNDR、$335\rm mV_｛pp｝$线性输入范围和4.7-$\text｛G｝\Omega$输入阻抗，斩波频率降低$64\times$。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量