Optimization of Ground-via Patterns for via Transitions by Minimizing Loop Inductance

Abstract

Via is a commonly used interconnect structure for vertically connecting signal traces or power or ground planes in packages and boards. As the speed of data transfer increases, the electrical properties of via structure becomes more and more important for getting better signal quality. Modeling a via structure typically involves complex computation. In this article, authors use partial element method to model the structure as coupled inductor array. It first proves that the loop inductance of a single-ended via transition is minimized through perturbation analysis. On the other hand, the differential-mode loop inductance of a via pair surrounded by 2, 4, 6, and 8 ground vias, respectively, is also derived. The full-wave simulation results all show good agreement with the ones predicted by formulae. Thus, with these formulae, the optimization of ground-via placement could be quickly found.