{"title":"Defect Localization Approach for Wafer-to-Wafer Hybrid Bonding Interconnects","authors":"Kristof J. P. Jacobs;Eric Beyne","doi":"10.1109/TSM.2023.3311452","DOIUrl":null,"url":null,"abstract":"A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid immersion lens. The top silicon substrate is removed using laser lithography and selective etching techniques, enabling the utilization of 405 nm excitation light for the VL-OBIRCH analysis. The validity of the methodology is demonstrated on W2W interconnect test structures with varying interconnect pitch and pad dimensions. The effectiveness of the proposed approach is confirmed through cross-sectional analysis.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"673-675"},"PeriodicalIF":2.3000,"publicationDate":"2023-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Semiconductor Manufacturing","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10239113/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid immersion lens. The top silicon substrate is removed using laser lithography and selective etching techniques, enabling the utilization of 405 nm excitation light for the VL-OBIRCH analysis. The validity of the methodology is demonstrated on W2W interconnect test structures with varying interconnect pitch and pad dimensions. The effectiveness of the proposed approach is confirmed through cross-sectional analysis.
期刊介绍:
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.