Reliability Implications of NBTI in Digital Integrated Circuits

Abstract

Bias temperature instability (BTI) in MOSFETs in one of the major reliability challenges in nano-scale technology. This paper evaluates the severity of Negative BTI (NBTI) degradation in two major circuit applications: random logic and memory array. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. Simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memories results in severe READ stability degradation, especially when combined with random process variation. Moreover, in scaled technology nodes, finite number of Si-H bonds in the channel can induce a statistical random variation in the degradation process. Simulations using 32nm/22nm Predictive Technology Model (PTM) shows that statistical random variation of NBTI, on top of random dopant fluctuation (RDF) results in significant random Vt variation in PMOS transistors, resulting in considerable degradation in static noise margin (SNM) of memory cells.