Modeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation

L. Milor
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引用次数: 0

Abstract

Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45nm technology test chip to relate geometry to failure rate statistics for low-k dielectric breakdown. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to determine if low-k materials satisfy lifetime requirements in the presence of die-to-die linewidth variation.
存在多种特征几何形状和模对模线宽变化的低k介电击穿建模
芯片上的后端几何图形包含各种各样的特征。本文分析了在45nm技术测试芯片上实现的测试结构的数据,以将几何形状与低k介电击穿的故障率统计联系起来。建立了考虑模间线宽变化的面积缩放模型,并提出了一种在模间线宽变化情况下确定低k材料是否满足寿命要求的方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Design & Test of Computers
IEEE Design & Test of Computers 工程技术-工程:电子与电气
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