A Novel Simulation Fault Injection using Electronic Systems Level Simulation Models

Abstract

Abstract—In this paper, we propose a novel simulation fault injection method for the dependability analysis of complex SoCs using 32 nm technology. In previous simulation fault injections, the original simulation model is modified to implement a saboteur module or many mutants. This creates a problem since the architectural complexity of current SoCs is expected to increase rapidly in the 32 nm era. Furthermore, the modification process may incur additional tasks, such as verification and validation of the modified simulation model. Our simulation fault injection environment uses the modified SystemC simulation kernel augmented for fault injection experiments. The proposed methodology offers the following advantages over previous simulation fault injection methods. First, it does not require changes in the target simulation design model. Second, it minimizes the simulation hardware resource requirements and simulation time. Third, it allows mixed simulation of the ESL model and the register transfer level model using wrappers. To demonstrate the effectiveness of the proposed methodology, we designed the SystemC models of MIPS and TMR MIPS processors and ran the benchmark SW from MiBench to compare the failure rates of the two processors.