Low-area architecture design of multi-mode activation functions with controllable maximum absolute error for neural network applications

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems Pub Date : 2023-10-11 DOI:10.1016/j.micpro.2023.104952

Shu-Yen Lin, Jung-Chuan Chiang

引用次数: 0

Abstract

In the development of the neural network (NN), the activation function has become more and more important. The selection of the activation function indirectly affects the convergence speed and accuracy. This study proposes the multi-mode activation function design (MMAFD) based on the least square method (LSM) with a controllable maximum absolute error (MAE) to support multiple activation functions. MMAFD selects the activation function to maintain the accuracy for different deep learning applications. MMAFD is implemented by TSMC 90 nm CMOS technology. In MMAFD, the power consumption is 0.98 mW, the operational frequency is 250 MHz, and the area is 0.416mm². MMAFD is also verified by Xilinx Spartan-6 XC6SLX45 development board. Compared to the related works verified in the FPGA boards, the LUTs and slices registers are reduced by up to 62.96 % and 73.90 %.

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神经网络应用中具有可控最大绝对误差的多模激活函数的低面积结构设计

在神经网络的发展过程中，激活函数变得越来越重要。激活函数的选择间接影响收敛速度和精度。本研究提出了基于具有可控最大绝对误差（MAE）的最小二乘法的多模式激活函数设计（MMAFD），以支持多个激活函数。MMAFD选择激活函数来保持不同深度学习应用程序的准确性。MMAFD采用TSMC 90nm CMOS技术实现。在MMAFD中，功耗为0.98mW，工作频率为250MHz，面积为0.416mm²。MMAFD也经过Xilinx Spartan-6 XC6SLX45开发板的验证。与在FPGA板上验证的相关工作相比，LUT和片寄存器分别减少了62.96%和73.90%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microprocessors and Microsystems 工程技术-工程：电子与电气

CiteScore

6.90

自引率

3.80%

发文量

204

审稿时长

172 days

期刊介绍： Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.