{"title":"Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication","authors":"Haibo Yang, Fengwei Dai, Liqiang Cao, Guofu Cao, Zhidan Fang, Qidong Wang","doi":"10.1108/mi-07-2022-0139","DOIUrl":null,"url":null,"abstract":"\nPurpose\nA large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.\n\n\nDesign/methodology/approach\nThis paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).\n\n\nFindings\nThe fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.\n\n\nOriginality/value\nThis paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.\n","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":" ","pages":""},"PeriodicalIF":0.7000,"publicationDate":"2023-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics International","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1108/mi-07-2022-0139","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Purpose
A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.
Design/methodology/approach
This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).
Findings
The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.
Originality/value
This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.
期刊介绍:
Microelectronics International provides an authoritative, international and independent forum for the critical evaluation and dissemination of research and development, applications, processes and current practices relating to advanced packaging, micro-circuit engineering, interconnection, semiconductor technology and systems engineering. It represents a current, comprehensive and practical information tool. The Editor, Dr John Atkinson, welcomes contributions to the journal including technical papers, research papers, case studies and review papers for publication. Please view the Author Guidelines for further details.
Microelectronics International comprises a multi-disciplinary study of the key technologies and related issues associated with the design, manufacture, assembly and various applications of miniaturized electronic devices and advanced packages. Among the broad range of topics covered are:
• Advanced packaging
• Ceramics
• Chip attachment
• Chip on board (COB)
• Chip scale packaging
• Flexible substrates
• MEMS
• Micro-circuit technology
• Microelectronic materials
• Multichip modules (MCMs)
• Organic/polymer electronics
• Printed electronics
• Semiconductor technology
• Solid state sensors
• Thermal management
• Thick/thin film technology
• Wafer scale processing.