Surface quality prediction and lapping process optimisation on the fixed-abrasive lapping plate of sapphire wafers

IF 0.7 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Yanfu Wang, X. Wang, Lifei Liu
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引用次数: 0

Abstract

Purpose Lapping is a vital flattening process to improve the quality of processed semiconductor wafers such as single-crystal sapphire wafers. This study aims to optimise the lapping process of the fixed-abrasive lapping plate of sapphire wafers with good overall performance [i.e. high material removal rate (MRR), small surface roughness (Ra) of the wafers after lapping and small lapping plate wear ratio (η)]. Design/methodology/approach The influence of process parameters such as lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed on MRR, Ra and η of lapping-processed sapphire wafers was studied, and the results were combined with experimental data to establish a regression model. The multi-evaluation index optimisation problem was transformed into a single-index optimisation problem via an entropy method and the grey relational analysis (GRA) to comprehensively evaluate the performance of each parameter. Findings The results revealed that lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed had different influence degrees on MRR, Ra and η. Among these parameters, lapping time, lapping speed and abrasive size had the most significant effects on MRR, Ra and η, and the established regression equations predicted the response values of MRR, Ra and η to be 99.56%, 99.51% and 93.88% and the relative errors between the predicted and actual measured values were <12%, respectively. With increased lapping time, MRR, Ra and η gradually decreased. With increased abrasive size, MRR increased nearly linearly, whereas Ra and η initially decreased but subsequently increased. With an increase in abrasive concentration, MRR, Ra and η initially increased but subsequently decreased. With increased lapping pressure, MRR and η increased nearly linearly and continuously, whereas Ra decreased nearly linearly and continuously. With increased lapping speed, Ra initially decreased sharply but subsequently increased gradually, whereas η initially increased sharply but subsequently decreased gradually; however, the change in MRR was not significant. Comparing the optimised results obtained via the analysis of influence law, the parameters optimised via the entropy method and GRA were used to obtain sapphire wafers lapping with an MRR of 4.26 µm/min, Ra of 0.141 µm and η of 25.08, and the lapping effect was significantly improved. Originality/value Therefore, GRA can provide new ideas for ultra-precision processing and process optimisation of semiconductor materials such as sapphire wafers.
蓝宝石晶片固定研磨研磨板表面质量预测及研磨工艺优化
铺平是提高单晶蓝宝石等半导体晶圆加工质量的重要铺平工艺。本研究旨在优化蓝宝石晶圆固定磨料研磨板的研磨工艺,使其具有良好的综合性能[即材料去除率(MRR)高,研磨后晶圆表面粗糙度(Ra)小,研磨板磨损比(η)小]。研究了研磨时间、磨料粒度、研磨浓度、研磨压力和研磨速度等工艺参数对蓝宝石晶圆MRR、Ra和η的影响,并将结果与实验数据相结合,建立了回归模型。通过熵值法和灰色关联分析(GRA)对各参数的性能进行综合评价,将多评价指标优化问题转化为单指标优化问题。结果表明:研磨时间、磨料粒度、研磨浓度、研磨压力和研磨速度对MRR、Ra和η均有不同程度的影响。其中,研磨时间、研磨速度和磨料粒度对MRR、Ra和η的影响最为显著,建立的回归方程预测MRR、Ra和η的响应值分别为99.56%、99.51%和93.88%,预测值与实测值的相对误差均小于12%。随着研磨时间的延长,MRR、Ra和η值逐渐降低。随着磨粒尺寸的增大,MRR呈线性增加,Ra和η先减小后增大。随着磨料浓度的增加,MRR、Ra和η先增大后减小。随着研磨压力的增加,MRR和η呈线性连续增加,Ra呈线性连续下降。随着研磨速度的增加,Ra先急剧减小后逐渐增大,η先急剧增大后逐渐减小;然而,MRR的变化并不显著。通过对影响规律分析得到的优化结果进行比较,将优化后的参数与GRA相结合,得到了MRR为4.26µm/min、Ra为0.141µm、η为25.08的蓝宝石晶圆研磨,研磨效果显著提高。因此,GRA可以为蓝宝石晶圆等半导体材料的超精密加工和工艺优化提供新的思路。
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来源期刊
Microelectronics International
Microelectronics International 工程技术-材料科学:综合
CiteScore
1.90
自引率
9.10%
发文量
28
审稿时长
>12 weeks
期刊介绍: Microelectronics International provides an authoritative, international and independent forum for the critical evaluation and dissemination of research and development, applications, processes and current practices relating to advanced packaging, micro-circuit engineering, interconnection, semiconductor technology and systems engineering. It represents a current, comprehensive and practical information tool. The Editor, Dr John Atkinson, welcomes contributions to the journal including technical papers, research papers, case studies and review papers for publication. Please view the Author Guidelines for further details. Microelectronics International comprises a multi-disciplinary study of the key technologies and related issues associated with the design, manufacture, assembly and various applications of miniaturized electronic devices and advanced packages. Among the broad range of topics covered are: • Advanced packaging • Ceramics • Chip attachment • Chip on board (COB) • Chip scale packaging • Flexible substrates • MEMS • Micro-circuit technology • Microelectronic materials • Multichip modules (MCMs) • Organic/polymer electronics • Printed electronics • Semiconductor technology • Solid state sensors • Thermal management • Thick/thin film technology • Wafer scale processing.
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