Influence of different etching methods on the structural properties of porous silicon

IF 0.7 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Fatimah Zulkifli, R. Radzali, A. F. Abd Rahim, A. Mahmood, N. S. Mohd Razali, Aslina Abu Bakar
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引用次数: 1

Abstract

Purpose Porous silicon (Si) was fabricated by using three different wet etching methods, namely, direct current photo-assisted electrochemical (DCPEC), alternating CPEC (ACPEC) and two-step ACPEC etching. This study aims to investigate the structural properties of porous structures formed by using these etching methods and to identify which etching method works best. Design/methodology/approach Si n(100) was used to fabricate porous Si using three different etching methods (DCPEC, ACPEC and two-step ACPEC). All the samples were etched with the same current density and etching duration. The samples were etched by using hydrofluoric acid-based electrolytes under the illumination of an incandescent lamp. Findings Field emission scanning electron microscopy (FESEM) images showed that porous Si etched using the two-step ACPEC method has a higher porosity and density than porous Si etched using DCPEC and ACPEC. The atomic force microscopy results supported the FESEM results showing that porous Si etched using the two-step ACPEC method has the highest surface roughness relative to the samples produced using the other two methods. High resolution X-ray diffraction revealed that porous Si produced through two-step ACPEC has the highest peak intensity out of the three porous Si samples suggesting an improvement in pore uniformity with a better crystalline quality. Originality/value Two-step ACPEC method is a fairly new etching method and many of its fundamental properties are yet to be established. This work presents a comparison of the effect of these three different etching methods on the structural properties of Si. The results obtained indicated that the two-step ACPEC method produced an etched sample with a higher porosity, pore density, surface roughness, improvement in uniformity of pores and better crystalline quality than the other etching methods.
不同蚀刻方法对多孔硅结构性能的影响
目的采用直流光辅助电化学(DCPEC)、交替CPEC(ACPEC)和两步ACPEC湿法刻蚀三种不同的湿法刻蚀方法制备多孔硅。本研究旨在研究使用这些蚀刻方法形成的多孔结构的结构特性,并确定哪种蚀刻方法最有效。设计/方法/方法使用Sin(100)使用三种不同的蚀刻方法(DCPEC、ACPEC和两步ACPEC)制备多孔硅。以相同的电流密度和蚀刻持续时间蚀刻所有样品。通过在白炽灯的照射下使用基于氢氟酸的电解质蚀刻样品。发现场发射扫描电子显微镜(FESEM)图像显示,使用两步ACPEC方法蚀刻的多孔硅比使用DCPEC和ACPEC蚀刻的多孔Si具有更高的孔隙率和密度。原子力显微镜结果支持FESEM结果,表明使用两步ACPEC方法蚀刻的多孔硅相对于使用其他两种方法生产的样品具有最高的表面粗糙度。高分辨率X射线衍射显示,在三个多孔硅样品中,通过两步ACPEC生产的多孔硅具有最高的峰值强度,这表明孔均匀性得到改善,结晶质量更好。独创性/价值两步ACPEC法是一种相当新的蚀刻方法,其许多基本特性尚待确定。比较了这三种不同蚀刻方法对硅结构性能的影响。结果表明,与其他蚀刻方法相比,两步ACPEC方法制备的蚀刻样品具有更高的孔隙率、孔密度、表面粗糙度、孔均匀性的改善和更好的结晶质量。
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来源期刊
Microelectronics International
Microelectronics International 工程技术-材料科学:综合
CiteScore
1.90
自引率
9.10%
发文量
28
审稿时长
>12 weeks
期刊介绍: Microelectronics International provides an authoritative, international and independent forum for the critical evaluation and dissemination of research and development, applications, processes and current practices relating to advanced packaging, micro-circuit engineering, interconnection, semiconductor technology and systems engineering. It represents a current, comprehensive and practical information tool. The Editor, Dr John Atkinson, welcomes contributions to the journal including technical papers, research papers, case studies and review papers for publication. Please view the Author Guidelines for further details. Microelectronics International comprises a multi-disciplinary study of the key technologies and related issues associated with the design, manufacture, assembly and various applications of miniaturized electronic devices and advanced packages. Among the broad range of topics covered are: • Advanced packaging • Ceramics • Chip attachment • Chip on board (COB) • Chip scale packaging • Flexible substrates • MEMS • Micro-circuit technology • Microelectronic materials • Multichip modules (MCMs) • Organic/polymer electronics • Printed electronics • Semiconductor technology • Solid state sensors • Thermal management • Thick/thin film technology • Wafer scale processing.
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