Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2022-11-14 DOI:10.1109/TDMR.2022.3221806

Pramod Kumar Patel;Manzar Malik;Tarun Kumar Gupta

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引用次数: 2

Abstract

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by

$2.67\mathbf {\times }$

and

$4.14\mathbf {\times }$

, respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by

$4161\mathbf {\times }$

when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.

查看原文本刊更多论文

基于gnrfet的可靠低漏9T SRAM优化技术

在这项研究中，我们提出了一种基于低泄漏石墨烯纳米带晶体管(gnrfet)的16nm技术静态随机存取存储器(SRAM)单元，该单元在亚阈值区域附近工作。与传统的Si-CMOS技术相比，该电池的读取稳定性和可写性分别提高了$2.67\mathbf {\times}$和$4.14\mathbf {\times}$。根据HSPICE模拟，所提出的单元在功耗、延迟、读取稳定性和可写性方面大大优于现有的9T sram单元。此外，在325mV的低电源电压下，采用多阈值方法和晶体管优化来提高读静态噪声裕度(RSNM)。当在写端口中使用多阈值方法时，与传统的6T SRAM单元相比，所提出的单元的总功耗降低了4161\mathbf {\times}$。设备优化和多阈值方法提高了读写性能，可以大大减少读写延迟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.