SOI FinFET Design Optimization for Radiation Hardening and Performance Enhancement

Abstract

This work proposes Total Ionizing Dose (TID) hardening techniques compatible with conventional 14-nm-node silicon-on-insulator (SOI) FinFETs’ process flows through performing 3-dimensional (3-D) simulations based on technology computer-aided design (TCAD) tools. The simulation results reveal a significantly critical TID impact induced by trapped charges in the buried oxide (BOX) and the spacer with calibration against 14 nm SOI FinFET’s experimental data (error ¡ 6%). Inspired by the physical interpretation, an optimization technique featuring an optimized gate structure, spacer length, and substrate bias is designed. The optimized gate structure is utilized to enhance the local gate-to-channel coupling at the bottom and reduce the generation and capture of electron-hole pairs. By reducing the spacer length, a lower sensitive volume in the spacer can effectively suppress the TID response. The setting of the negative substrate bias greatly improves the subthreshold characteristics, weakening the TID effect in the BOX. By adopting the combined optimization including these techniques, the threshold voltage shift $(\Delta V_{\mathrm{ TH}})$ induced by a 5 Mrad(SiO2) irradiation can be reduced to 21 mV, whereas $\Delta V_{\mathrm{ TH}}$ is 45 mV with only gate structure optimized and 97 mV without hardening. Meanwhile, the $I_{\mathrm{ ON}}/I_{\mathrm{ OFF}}$ after radiation increases to $1\times 10\,\,^{\mathrm{ 7}}$ , which is at least four orders of magnitude better than the original device. Meanwhile, subthreshold swing (SS) is reduced from 81 mV/dec to 71 mV/dec, and Drain Induced Barrier Lowering (DIBL) is reduced from 120 mV/V to 99 mV/V, respectively. The combined optimization design is demonstrated as an effective method to improve the tolerance against TID irradiation without compromising performance, promoting 14 nm SOI FinFET’s application in future harsh space environments.