Zehao Wu;Jing Zhang;Zeqi Huang;Lei Shen;Minchi Hu;Wangshen Wen;Peiyu Li;Zongxuan Xie;Chang Cai
{"title":"Critical Node Sensitivity Analysis and High-Reliability Design for CNN Accelerators on 16-nm FPGA Devices","authors":"Zehao Wu;Jing Zhang;Zeqi Huang;Lei Shen;Minchi Hu;Wangshen Wen;Peiyu Li;Zongxuan Xie;Chang Cai","doi":"10.1109/TDMR.2026.3695152","DOIUrl":null,"url":null,"abstract":"In recent years, Convolutional Neural Networks (CNNs) have emerged as a cornerstone technology for image processing tasks in safety-critical domains. Although advanced Artificial Intelligence (AI) acceleration devices are ideal for space applications due to their high computational efficiency and flexibility, they remain highly susceptible to Single Event Upsets (SEUs) and are still constrained by limited resources. Thus, it becomes imperative to design CNN implementations for Field-Programmable Gate Array (FPGA) devices that achieve a delicate balance between low cost and high reliability. However, traditional hardening strategies often neglect the sensitivity of internal nodes, relying instead on global or coarse-grained module-level hardening strategies that significantly increase resource overhead and degrade timing performance. To address this issue, we propose a basic unit partitioning strategy that divides CNN accelerators into functionally independent circuit nodes. Within our fault analysis framework, we map fault locations to specific nodes using address mapping, enabling sensitivity analysis. Additionally, we implement fine-grained hardening on critical nodes identified through sensitivity analysis and compare this strategy against module-level coarse-grained hardening and full triple modular redundancy (TMR) strategies. Fault analysis results reveal that our strategy delivers excellent hardening effectiveness at a reduced cost. Our strategy achieves a 31.9% reduction in resource overhead and a 29.9% improvement in timing performance compared to Full_TMR, with comparable fault tolerance. Compared to module-level hardening strategies, our approach achieves higher hardening efficiency. The irradiation experiment results further validate the effectiveness of our strategy, achieving a <inline-formula> <tex-math>$10.6\\times $ </tex-math></inline-formula> improvement in Mean Time To Failure (MTTF) compared to the unhardened baseline, which is comparable to that of full TMR. The proposed reliability evaluation method achieves high accuracy, with errors within ±4.3%. Overall, the proposed hardening strategy and reliability evaluation method present a significant advancement in designing robust and cost-effective systems, holding vast potential for adoption in safety-critical fields such as aerospace and autonomous driving.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"822-831"},"PeriodicalIF":2.7000,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11527364/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/3/20 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In recent years, Convolutional Neural Networks (CNNs) have emerged as a cornerstone technology for image processing tasks in safety-critical domains. Although advanced Artificial Intelligence (AI) acceleration devices are ideal for space applications due to their high computational efficiency and flexibility, they remain highly susceptible to Single Event Upsets (SEUs) and are still constrained by limited resources. Thus, it becomes imperative to design CNN implementations for Field-Programmable Gate Array (FPGA) devices that achieve a delicate balance between low cost and high reliability. However, traditional hardening strategies often neglect the sensitivity of internal nodes, relying instead on global or coarse-grained module-level hardening strategies that significantly increase resource overhead and degrade timing performance. To address this issue, we propose a basic unit partitioning strategy that divides CNN accelerators into functionally independent circuit nodes. Within our fault analysis framework, we map fault locations to specific nodes using address mapping, enabling sensitivity analysis. Additionally, we implement fine-grained hardening on critical nodes identified through sensitivity analysis and compare this strategy against module-level coarse-grained hardening and full triple modular redundancy (TMR) strategies. Fault analysis results reveal that our strategy delivers excellent hardening effectiveness at a reduced cost. Our strategy achieves a 31.9% reduction in resource overhead and a 29.9% improvement in timing performance compared to Full_TMR, with comparable fault tolerance. Compared to module-level hardening strategies, our approach achieves higher hardening efficiency. The irradiation experiment results further validate the effectiveness of our strategy, achieving a $10.6\times $ improvement in Mean Time To Failure (MTTF) compared to the unhardened baseline, which is comparable to that of full TMR. The proposed reliability evaluation method achieves high accuracy, with errors within ±4.3%. Overall, the proposed hardening strategy and reliability evaluation method present a significant advancement in designing robust and cost-effective systems, holding vast potential for adoption in safety-critical fields such as aerospace and autonomous driving.
期刊介绍:
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.