Critical Node Sensitivity Analysis and High-Reliability Design for CNN Accelerators on 16-nm FPGA Devices

IF 2.7 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Zehao Wu;Jing Zhang;Zeqi Huang;Lei Shen;Minchi Hu;Wangshen Wen;Peiyu Li;Zongxuan Xie;Chang Cai
{"title":"Critical Node Sensitivity Analysis and High-Reliability Design for CNN Accelerators on 16-nm FPGA Devices","authors":"Zehao Wu;Jing Zhang;Zeqi Huang;Lei Shen;Minchi Hu;Wangshen Wen;Peiyu Li;Zongxuan Xie;Chang Cai","doi":"10.1109/TDMR.2026.3695152","DOIUrl":null,"url":null,"abstract":"In recent years, Convolutional Neural Networks (CNNs) have emerged as a cornerstone technology for image processing tasks in safety-critical domains. Although advanced Artificial Intelligence (AI) acceleration devices are ideal for space applications due to their high computational efficiency and flexibility, they remain highly susceptible to Single Event Upsets (SEUs) and are still constrained by limited resources. Thus, it becomes imperative to design CNN implementations for Field-Programmable Gate Array (FPGA) devices that achieve a delicate balance between low cost and high reliability. However, traditional hardening strategies often neglect the sensitivity of internal nodes, relying instead on global or coarse-grained module-level hardening strategies that significantly increase resource overhead and degrade timing performance. To address this issue, we propose a basic unit partitioning strategy that divides CNN accelerators into functionally independent circuit nodes. Within our fault analysis framework, we map fault locations to specific nodes using address mapping, enabling sensitivity analysis. Additionally, we implement fine-grained hardening on critical nodes identified through sensitivity analysis and compare this strategy against module-level coarse-grained hardening and full triple modular redundancy (TMR) strategies. Fault analysis results reveal that our strategy delivers excellent hardening effectiveness at a reduced cost. Our strategy achieves a 31.9% reduction in resource overhead and a 29.9% improvement in timing performance compared to Full_TMR, with comparable fault tolerance. Compared to module-level hardening strategies, our approach achieves higher hardening efficiency. The irradiation experiment results further validate the effectiveness of our strategy, achieving a <inline-formula> <tex-math>$10.6\\times $ </tex-math></inline-formula> improvement in Mean Time To Failure (MTTF) compared to the unhardened baseline, which is comparable to that of full TMR. The proposed reliability evaluation method achieves high accuracy, with errors within ±4.3%. Overall, the proposed hardening strategy and reliability evaluation method present a significant advancement in designing robust and cost-effective systems, holding vast potential for adoption in safety-critical fields such as aerospace and autonomous driving.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"822-831"},"PeriodicalIF":2.7000,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11527364/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/3/20 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

In recent years, Convolutional Neural Networks (CNNs) have emerged as a cornerstone technology for image processing tasks in safety-critical domains. Although advanced Artificial Intelligence (AI) acceleration devices are ideal for space applications due to their high computational efficiency and flexibility, they remain highly susceptible to Single Event Upsets (SEUs) and are still constrained by limited resources. Thus, it becomes imperative to design CNN implementations for Field-Programmable Gate Array (FPGA) devices that achieve a delicate balance between low cost and high reliability. However, traditional hardening strategies often neglect the sensitivity of internal nodes, relying instead on global or coarse-grained module-level hardening strategies that significantly increase resource overhead and degrade timing performance. To address this issue, we propose a basic unit partitioning strategy that divides CNN accelerators into functionally independent circuit nodes. Within our fault analysis framework, we map fault locations to specific nodes using address mapping, enabling sensitivity analysis. Additionally, we implement fine-grained hardening on critical nodes identified through sensitivity analysis and compare this strategy against module-level coarse-grained hardening and full triple modular redundancy (TMR) strategies. Fault analysis results reveal that our strategy delivers excellent hardening effectiveness at a reduced cost. Our strategy achieves a 31.9% reduction in resource overhead and a 29.9% improvement in timing performance compared to Full_TMR, with comparable fault tolerance. Compared to module-level hardening strategies, our approach achieves higher hardening efficiency. The irradiation experiment results further validate the effectiveness of our strategy, achieving a $10.6\times $ improvement in Mean Time To Failure (MTTF) compared to the unhardened baseline, which is comparable to that of full TMR. The proposed reliability evaluation method achieves high accuracy, with errors within ±4.3%. Overall, the proposed hardening strategy and reliability evaluation method present a significant advancement in designing robust and cost-effective systems, holding vast potential for adoption in safety-critical fields such as aerospace and autonomous driving.
基于16nm FPGA器件的CNN加速器关键节点灵敏度分析与高可靠性设计
近年来,卷积神经网络(cnn)已成为安全关键领域图像处理任务的基石技术。尽管先进的人工智能(AI)加速设备由于其高计算效率和灵活性而成为空间应用的理想选择,但它们仍然极易受到单事件干扰(seu)的影响,并且仍然受到有限资源的限制。因此,为现场可编程门阵列(FPGA)器件设计CNN实现,以实现低成本和高可靠性之间的微妙平衡,变得势在必行。然而,传统的强化策略往往忽略了内部节点的敏感性,而是依赖于全局或粗粒度的模块级强化策略,这会显著增加资源开销并降低定时性能。为了解决这个问题,我们提出了一种基本的单元划分策略,将CNN加速器划分为功能独立的电路节点。在我们的故障分析框架中,我们使用地址映射将故障位置映射到特定节点,从而实现灵敏度分析。此外,我们在通过灵敏度分析确定的关键节点上实现了细粒度强化,并将该策略与模块级粗粒度强化和全三模块冗余(TMR)策略进行了比较。故障分析结果表明,我们的策略以较低的成本提供了出色的硬化效果。与Full_TMR相比,我们的策略减少了31.9%的资源开销,提高了29.9%的定时性能,并具有相当的容错性。与模块级硬化策略相比,我们的方法具有更高的硬化效率。辐照实验结果进一步验证了我们策略的有效性,与未硬化基线相比,平均故障时间(MTTF)提高了10.6倍,与全TMR相当。所提出的可靠性评估方法精度较高,误差在±4.3%以内。总体而言,所提出的强化策略和可靠性评估方法在设计稳健且具有成本效益的系统方面取得了重大进展,在航空航天和自动驾驶等安全关键领域具有巨大的应用潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability 工程技术-工程:电子与电气
CiteScore
4.80
自引率
5.00%
发文量
71
审稿时长
6-12 weeks
期刊介绍: The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信
小红书