Fast Heater-Based NBTI Resolves the Reverse Antenna Effect in PID-Degraded High-k and SiO2 pMOSFETs

Abstract

Plasma-induced charging damage (PID) introduces additional trapping sites in gate dielectrics and can distort negative bias temperature instability (NBTI) characterization when measured with conventional hot-chuck routines. We present a fast heater-based NBTI methodology that integrates local polysilicon heaters with rapid readout to minimize the delay between stress and threshold-voltage $V_{\mathrm {t}}$ measurement and to quench devices to near room temperature within the early-millisecond window. Applied to pMOSFETs with SiO₂ and high- $k$ gate stacks bearing stacked-antenna structures, the fast routine captures larger threshold-voltage shifts $\Delta V_{\mathrm {t}}$ than the conventional routine while preserving the antenna ratio (AR) trend in SiO₂. In SiO₂, $\Delta V_{\mathrm {t}}$ increases with AR under both routines, with the fast routine producing a uniform ~8-10 mV offset at matched times; diode-protected controls show no $\Delta V_{\mathrm {t}}$ increase with antenna size, confirming suppression of PID. In high- $k$ devices, the apparent antenna effect is strongly routine-dependent: the conventional routine at 125°C exhibits a mild reverse antenna effect (antenna $\Delta V_{\mathrm {t}} \lt $ reference), whereas the fast routine reveals larger immediate post-stress $\Delta V_{\mathrm {t}}$ in antenna devices. Pre-stress $V_{\mathrm {t}}$ measurements vs temperature $T$ and early recovery data (~1-6 ms) indicate co-existing trap populations—fast, shallow positive-charge traps and slower, deep negative-charge traps—whose interplay explains the routine-dependent behavior and resolves the reverse antenna effect without post-hoc data correction. These results demonstrate that fast heater-based NBTI more faithfully probes the instantaneous post-stress state and improves reliability assessment in PID-susceptible technologies.