A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing

Abstract

In-sensor computing (ISC) based on amorphous metal-oxide thin-film transistors (TFTs) promises compact, high-density vision chips, yet large-scale integration is vulnerable to process-induced threshold-voltage ( $V_{th}$ ) variations that critically degrade computational robustness and accuracy. This work proposes a novel 3T1C (3-Transistor, 1-Capacitor) ISC cell circuit based on photodiode (PD)-gated dual-gate (DG) indium-gallium-zinc-oxide (IGZO) TFTs featuring a $V_{th}$ self-compensating mechanism for enhanced robustness. The proposed circuit seamlessly integrates memory storage, sensor, and multiply-accumulate (MAC) operations into a single compact cell with a self-compensated sense TFT introduced to effectively suppress the $V_{th}$ variation during the computing phase. Using a neural-network-based device model, SPICE simulations to validate circuit functionality are performed, presenting a $2\times $ to $3\times $ reduction in computing current variation compared to uncompensated baselines, along with excellent MAC linearity. System-level evaluation of a VGG8 network on CIFAR-10 demonstrates negligible accuracy loss relative to an ideal software implementation. This work validates the feasibility of highly accurate robust ISC on inherently large-scale TFT arrays, offering a practical path toward large-area, low-cost ISC arrays for edge intelligence applications.