Experimental Evidence for the Impact of Copper Microstructure on Residual Stress of Through Silicon Via

Abstract

Three-dimensional integrated circuits (3DICs) with Cu through silicon vias (TSVs) offer improved system performance beyond front-end-of-line scaling. However, the residual thermal stress imparted by TSVs on the surrounding silicon raises reliability concerns. This stress depends on the mechanical properties of Cu, which are governed by its underlying microstructure because of the metal's anisotropic elastic modulus. Smaller TSVs magnify this microstructural effect due to the increased grain-to-via diameter ratio. Here, we experimentally quantify the impact of Cu microstructure on the TSV-induced residual stress within silicon. A 3-$\mu m$-diameter TSV array was annealed at 400${}^{\circ }C$ for 60 min, and the residual stress in the surrounding Si was imaged with Raman spectroscopy at room temperature. The Cu surface microstructure was characterized with electron backscatter diffraction (EBSD) to deduce the microstructure dependent effective elastic modulus. Mean Si residual stress increased with the out-of-plane effective elastic modulus of Cu, which varies by a factor of 2 with the grain structure, and the microstructural influence diminishes with increasing distance from the TSV. Together, these findings provide direct experimental evidence linking copper microstructure to the residual stress within the Si near a TSV, an effect that becomes increasingly prominent with the continued TSV scaling.