Location-Selective Dual Work-Function Engineering for DRAM Vertical Cell Transistors

Abstract

As dynamic random-access memory (DRAM) technology approaches the scaling limit of conventional 6F² buried-channel array transistor (BCAT) structures, vertical cell transistors (VCTs) have emerged as promising candidates for future 4F² DRAM architectures. In this work, a location-selective Dual Work-Function (DWF) engineering scheme is proposed to co-optimize leakage and drive-current characteristics in VCT devices. Using calibrated three-dimensional TCAD simulations, lower-work-function n+ polysilicon regions were selectively introduced into the front-gate (FG) and back-gate (BG) electrodes. In the buried contact (BC)-side DWF implementation, the local gate electrostatics near the BC junction were modulated, thereby reducing the peak electric field responsible for gate-induced drain leakage (GIDL). The FG_BC DWF reduced GIDL current by up to 66% while maintaining a threshold voltage (V ${}_{\text {T}}\text {)}$ shift below 10 mV and less than 1% variation in ON-current. In the bit line (BL)-side DWF implementation, the reduced work function lowered the electron injection barrier near the BL-side carrier-injection region, leading to ON-current enhancement of up to 12.6% while maintaining nearly unchanged V_T and subthreshold swing (SS). In addition, a combined FG_BC+BG_BL structure demonstrated concurrent GIDL suppression and ON-current enhancement without additional WL resistance overhead. These results indicate that location-selective DWF engineering, enabled by the vertically separated BC-side and BL-side junctions, provides a promising design guideline for low-leakage and high-performance 4F² DRAM VCTs.