High-Performance S/D-First IGZO TFTs Integrated With p-Type Si Nanowire FETs for Complementary Logic

Abstract

High-performance complementary logic requires process-compatible n-type and p-type devices with low degradation. Here, we report the heterogeneous integration of source/drain-first (S/D-first) IGZO TFTs with in-plane solid–liquid–solid (IPSLS)-grown p-type Si nanowire (SiNW) FETs for complementary logic. The S/D-first process effectively suppresses lithography-induced channel damage, thereby enabling that the field-effect mobility of IGZO TFT increases to 31.4 cm² V^-1 s^-1, while the subthreshold swing decreases 166 mV dec^-1. Meanwhile, the p-SiNW FETs exhibit a field-effect mobility of 54 cm² V^-1 s^-1 and a subthreshold swing of ~117 mV dec^-1. Based on these complementary devices, low-power inverters as well as NOR, NAND, and AND logic gates are demonstrated, confirming the feasibility of combing the n-IGZO TFTs and p-SiNW FETs for heterogeneous complementary logic integration.