A Comprehensive Design Framework for Vertical Power Delivery in High-Performance Computing

Abstract

Power delivery—including high-to-low voltage conversion, complex power distribution across heterogeneously integrated chiplets, and efficient interconnect allocation—remains a critical bottleneck in high-performance computing (HPC) systems. Existing vertical power-delivery (VPD) solutions are estimated to achieve less than 70% system-wide end-to-end power-delivery efficiency, defined from platform input power to delivered on-chip load power, with substantial energy lost as heat before reaching on-chip point-of-loads (POLs). In the absence of systematic design methodologies, evaluating power quality, exploring architectural alternatives, and optimizing performance rely on computationally prohibitive simulations, resulting in suboptimal designs. This article introduces an end-to-end scalable power-delivery framework for HPC systems, including distributed VPD (DVPD) architecture, DVPD design optimization methodology, and analytical models. The framework leverages substrate-embedded GaN power switches together with arrays of unit inductors and capacitors tailored for HPC applications. Multistage power conversion schemes (48-to-1 V, 48-to-24-to-1 V, and 48-to-12-to-1 V) are explored, with system-wide voltage drops and power losses evaluated under steady-state conditions. Design specifications for passive and active devices are formulated to meet next-generation efficiency targets. For the 48-to-1 V case, the proposed DVPD approach achieves 84% system-wide efficiency while occupying 54% of the area beneath the load system, with efficiency increasing to 87.6% at 75% area utilization across a 1–50 kW load range. Furthermore, steady-state voltage drops peak at 2.7% and transient drops at 9% (without decoupling capacitors), demonstrating the viability of DVPD for future wafer-scale HPC platforms.