A Scalable Stress Recovery Technique for Hybrid Bonding in Chiplet-Based Systems

Abstract

The post-Moore era has ushered in the development of multichip and multistack chiplet-based systems, with hybrid bonding (HB) serving as a method to achieve ultrafine pitch interconnections. This article presents a scalable stress recovery technique designed for thermal–mechanics analysis of HB. Our method enhances the accuracy of $C^{-1}$ continuous stress on element boundaries within finite elements by employing postprocessing on the displacement-based finite-element method (FEM). This recovery technique focuses solely on solving local problems near the finite element, making it well-suited for deployment in multicore parallel application scenarios. We illustrate the effectiveness of this approach through numerical examples involving chip-to-wafer (C2W) and die-to-wafer (D2W) HB cases, analyzing its accuracy, efficiency, and scalability. Overall, our method demonstrates advantages over traditional approaches, achieving a 90.9% reduction in computational scale, a 95.4% decrease in running time, and a 44.5% reduction in memory usage, all while maintaining the same accuracy requirements. Furthermore, we evaluate the thousand-core parallel capability of this technique on a high-performance computing (HPC) platform, underscoring its application in simulating ultrahigh-density chiplet interconnections and evaluating the potential risk of bonding voids from simulation.