A Lossy Decoupling Network for Anti-Resonance Suppression and Capacitor Reduction in CoWoP

Abstract

Chip-on-wafer-on-platform (CoWoP) technology has recently been reported as a potential shift in the packaging technology for NVIDIA’s next-generation artificial intelligence (AI) GPUs for higher performance. CoWoP excludes package inductance and reduces the parasitic inductance of the voltage regulator module (VRM), which results in a fast and smaller printed circuit board (PCB) decoupling network. Small and fast decoupling networks are also accompanied by severe anti-resonance, causing unwanted sharp peaks in the frequency-domain impedance profile and voltage oscillations in the time-domain. The traditional target impedance design method leads to a larger number of decoupling capacitors for anti-resonance suppression. In this article, the anti-resonance-induced power noise of a multiple-capacitor decoupling network is studied first. It is recursively simplified to $n$ second-order systems, and then the resonant parameters of each loop are derived. The transient response exhibits two types of voltage droops: inductive/resistive voltage drops and anti-resonance-induced oscillations. According to the analysis, a new decoupling network design method is proposed, in which lossy components are introduced for anti-resonance suppression and capacitor reduction. Anti-resonance-induced power noise is analyzed under transient conditions first. Through simulation and experimental validation, the lossy decoupling strategy can not only improve the robustness and efficiency of decoupling networks but also reduce nearly two-thirds of component usage compared to conventional methods. Some practical design guidelines are developed to balance the voltage drop and the loop loss, ensuring reliable decoupling network performance in CoWoPs.