Investigation of High-Temperature Characteristics of GaN p-Channel Field-Effect Transistors at 200 °C

Abstract

GaN p-channel field-effect transistors (p-FETs) are essential for realizing efficient GaN complementary circuits. However, there has been limited research on the high-temperature reliability of GaN p-FETs. This article investigates the temperature dependence of GaN p-FETs. As temperature increases from $25~^{\circ }$ C to $200~^{\circ }$ C, the threshold voltage exhibits a negative shift from −1.79 to −2.02 V under forward scanning, while threshold voltage hysteresis increases from 0.77 to 2.17 V, and the maximum drain current declines from 0.015 to ${2.1} \times 10^{-{4}}$ mA/mm, with higher leakage current and lower $\text {I}_{\text {ON}}$ / ${I}_{\text {OFF}}$ ratio. This is primarily attributed to enhanced carrier transitions and scattering at high temperature, which further reduce the 2-D hole gas (2DHG) density and mobility. Furthermore, the threshold voltage shows a slight positive shift above $100~^{\circ }$ C during forward sweeping, which arises from enhanced acceptor ionization at elevated temperatures. Variable-temperature Hall-effect measurement shows mobility decreases from 12.79 to 4.62 cm2/V $\cdot $ s and effective hole density increases from ${4.85} \times {10}^{{12}}$ ${\mathrm{cm}}^{-{2}}$ to ${4.75} \times {10}^{{13}}$ ${\mathrm{cm}}^{-{2}}$ within this temperature range. Notably, after 24 h of recovery, the interface trap density ( $\text {D}_{\text {it}}$ ) decreases from 1.99~3.30 $\times {10}^{{13}}$ to 1.45~2.65 $\times {10}^{{13}}$ ${\mathrm{cm}}^{-{2}}$ /eV, and the trap energy levels become shallower, shifting from 0.41~0.44 to 0.36~0.38 eV. Accordingly, the drain current increases by 73% compared with its initial state. These results reveal substantial degradation in the electrical characteristics of the studied p-FET at temperatures up to $200~^{\circ }$ C, with basic recovery of electrical performance achievable after 24 h of room-temperature relaxation. This work delivers critical insights into the development of high-temperature operable GaN-based integrated complementary logic (CL) circuits.