Access-Induced Pass-Gate Bias Stress in Oxide-Semiconductor SRAM: Stress-Aware SPICE Analysis and SU-8 Passivation

Abstract

Oxide-semiconductor static random-access memory (SRAM) suffers from gate-bias-stress vulnerability in word-line (WL)-driven access thin-film transistors (TFTs). We identify row-level WL activation as an intrinsic “access-induced” stress source that also biases pass-gate TFTs in unselected cells within the same row. SnO and indium--gallium--zinc oxide (IGZO) TFTs are characterized and calibrated using Berkeley short-channel IGFET model--common multi-gate (BSIM-CMG), enabling stress-aware SPICE simulations. Positive bias stress (PBS) induces pronounced transfer-curve shifts in unpassivated IGZO pass-gate TFTs, while SU-8 passivation effectively suppresses the degradation. By incorporating PBS-calibrated pass-gate models into SRAM analysis, we observe a tradeoff in which the read static noise margin (RSNM) degrades, whereas the write noise margin (WNM) improves with stress time. Notably, when SU-8 passivation is applied to the pass-gate devices, the SRAM read/write margins exhibit minimal variation even under extended PBS. These results demonstrate, using SU-8 as a proof-of-concept (PoC) encapsulation, that suppressing pass-gate bias-stress drift is an effective strategy for stabilizing oxide semiconductor SRAM under repeated WL accesses.